The present invention relates to multipliers for use in data processing systems.
Low performance computers frequently perform multiplication by a sequence of additions using an adder. Such approach takes many cycles of operation and thus is slow. High performance computers cannot tolerate long routines for multiplication. Therefore, high performance data processing systems generally include special functional units and/or special high speed routines to handle multiplication.
In multiplication, multipliers and multiplicands can both be positive and negative. Frequently, 2's complement form is employed to accommodate negative numbers. There are many ways to design multipliers to handle 2's complement multipliers and multiplicands. In one approach, the signs of both operands (multiplier and multiplicand) can be checked prior to commencing the multiplication. Depending upon the signs of the operands, the appropriate multiplication routine is executed to give the correct, final product. While such a method is satisfactory for many applications, it has the detriment that the multiplication routine cannot commence until after the signs have been checked. Such a procedure always requires a delay before the multiplication commences and such delay is wasteful of processing time. In another approach, sign extension hardware is used which operates in parallel with other multiplication hardware thereby avoiding extra processing time. The sign extension hardware, however, has the detriment of adding extra cost and complexity to the computer.
In accordance with the above background, there is a need for an improved multiplier and method of multiplication in a data processing system which avoids the extra cost required with sign extension hardware and which avoids the delays required for sign checking prior to the time that multiplication begins.
In general, multipliers for high-performance systems must be able to multiply relatively large operands. For example, a typical multiplier should be large enough to multiply 32-bit signed operands to form a 64-bit signed product, and to multiply 56-bit unsigned operands to form 112-bit unsigned products. However, the physical size of the multiplier must be minimized, by taking advantage, for example, of hardware provided for other purposes.